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December 2010

NC7WZ16

TinyLogic^?UHS Dual Buffer

Features

Description

The NC7WZ16 is a dual buffer from Fairchild’s Ultra-

High Speed Series of TinyLogic^?. The device is

fabricated with advanced CMOS technology to achieve

ultra-high speed with high output drive while maintaining

low static power dissipation over a very broad V_CC

operating range. The device is specified to operate over

the 1.65V to 5.5V V_CCrange. The inputs and outputs are

high impedance when V_CCis 0V. Inputs tolerate

voltages up to 7V independent of V_CCoperating voltage.

?

Ultra-High Speed: t_PD2.4ns (Typical) into 50pF at

5V V_CC

?

High Output Drive: ±24mA at 3V V_CC

Broad V_CCOperating Range: 1.65V to 5.5V

Matches Performance of LCX when Operated at

3.3V V_CC

?

Power Down High-Impedance Inputs/Outputs

Over-Voltage Tolerance Inputs Facilitate 5V to 3V

Translation

?

Proprietary Noise/EMI Reduction Circuitry

Ultra-Small MicroPak? Packages

Space-Saving SC70 Package

Ordering Information

Part Number

NC7WZ16P6X

NC7WZ16L6X

NC7WZ16FHX

Top Mark

Package

Packing Method

Z16

C7

6-Lead SC70, EIAJ SC-88a, 1.25mm Wide

6-Lead MicroPak?, 1.00mm Wide

3000 Units on Tape & Reel

5000 Units on Tape & Reel

C7

6-Lead, MicroPak2?, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

Connection Diagrams

IEEC/IEC

Figure 1. Logic Symbol

Pin Configurations

Figure 2. SC70 (Top View)

Figure 3. MicroPak? (Top Through View)

Notes:

1. AAA represents Product Code Top Mark (see ordering code).

2. Orientation of Top Mark determines Pin One location. Read the top product code mark left to right.

Pin One is the lower left pin.

Figure 4. Pin 1 Orientation

Pin Definitions

Pin # SC70

Pin # MicroPak?

Name

A₁

Description

1

2

3

4

5

6

1

2

3

4

5

6

Input

GND

A₂

Ground

Input

Y₂

Output

V_CC

Y₁

Supply Voltage

Output

Function Table

Y= A

Inputs

Output

A

L

Y

L

H

H = HIGH Logic Level

L = LOW Logic Level

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

2

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

-0.5

Max.

7.0

Unit

V

Supply Voltage

V_IN

DC Input Voltage

7.0

V

V_OUT

I_IK

DC Output Voltage

7.0

V

DC Input Diode Current

DC Output Diode Current

DC Output Source / Sink Current

DC V_CCor Ground Current

Storage Temperature Range

Junction Temperature Under Bias

V_IN< 0V

V_OUT< 0V

-50

mA

°C

I_OK

-50

I_OUT

±50

I_CCor I_GND

T_STG

T_J

±100

+150

+260

180

-65

T_L

Junction Lead Temperature (Soldering, 10 Seconds)

SC70-6

P_D

Power Dissipation

MicroPak?-6

MicroPak2?-6

130

mW

V

120

Human Body Model, JEDEC:JESD22-A114

Charge Device Model, JEDEC:JESD22-C101

4000

2000

ESD

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Supply Voltage Operating

Supply Voltage Data Retention

Input Voltage

Conditions

Min.

1.65

1.50

0

Max.

5.50

5.5

Unit

V_CC

V

V_IN

V

V_OUT

Output Voltage

0

V_CC

20

V

_CC=1.8V, 2.5V ±0.2V

0

t_r,t_f

T_A

Input Rise and Fall Times

Operating Temperature

Thermal Resistance

V_CC=3.3V ±0.3V

V_CC=5.5V ±0.5V

0

10

ns/V

°C

0

5

-40

+125

425

500

560

SC70-6

MicroPak?-6

MicroPak2?-6

°C/W

θ_JA

Note:

3. Unused inputs must be held HIGH or LOW. They may not float.

? 1999 Fairchild Semiconductor Corporation

www.fairchildsemi.com

NC7WZ16 ? Rev. 1.0.4

3

DC Electrical Characteristics

T_A=25°C

Typ. Max.

T_A=-40 to +85°C

Symbol

Parameter

V_CC(V)

Conditions

Units

Min.

Max.

1.65 to 1.95

2.3 to 5.5

1.65 to 1.95

2.3 to 5.5

1.65

0.75V_CC

0.70V_CC

0.75V_CC

0.70 V_CC

HIGH Level Control

Input Voltage

V_IH

V_IL

V

0.25V_CC

0.30V_CC

0.25V_CC

0.30V_CC

LOW Level Control

Input Voltage

1.55

1.70

2.20

2.90

4.40

1.29

1.90

2.40

2.30

3.80

1.65

1.80

2.30

3.00

4.50

1.52

2.14

2.75

2.62

4.13

0.00

0.08

0.10

0.16

0.24

0.25

1.55

1.70

2.20

2.90

4.40

1.21

1.90

2.40

2.30

3.80

1.80

2.30

I

_OH=-100μA

3.00

4.50

HIGH Level Output

Voltage

V_OH

V_IN=V_IH

V

1.65

I_OH=-4mA

I_OH=-8mA

I_OH=-16mA

I_OH=-24mA

I_OH=-32mA

2.30

3.00

4.50

1.65

0.10

0.24

0.30

0.40

0.55

0.10

0.24

0.30

0.40

0.55

1.80

2.30

I

_OL=100μA

3.00

4.50

LOW Level Output

Voltage

V_OL

V_IN=V_IL

V

1.65

I_OL=4mA

I_OL=8mA

2.30

3.00

I_OL=16mA

I_OL=24mA

I_OL=32mA

3.00

4.50

Input Leakage

Current

I_IN

I_OFF

I_CC

0 to 5.5

0

±0.1

1.0

±1.0

10

μA

0 ≥ V_IN≥ 5.5V

Power Off Leakage

Current

V_INor V_OUT=5.5V

Quiescent Supply

Current

1.65 to 5.50 V_IN=5.5V, GND

1.0

10

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

4

AC Electrical Characteristics

T_A=25°C

T_A=-40 to +85°C

Symbol

Parameter

V_CC(V)

Conditions

Units Figure

Min. Typ. Max. Min.

Max.

1.65

1.80

1.8

1.0

0.8

0.5

1.2

0.8

5.5

4.6

3.0

2.3

1.8

3.0

2.4

2.5

10

9.6

8.0

5.2

3.6

2.9

4.6

3.8

1.8

1.0

0.8

0.5

1.2

0.8

10.6

8.8

5.8

4.0

3.2

5.1

4.2

C_L=15pF,

R_L=1MΩ

Figure 5

Figure 6

ns

2.50 ± 0.20

3.30 ± 0.30

5.00 ± 0.50

3.30 ± 0.30

5.00 ± 0.50

0.00

t_PLH, t_PHLPropagation Delay

C_L=50pF,

R_L=500Ω

Figure 5

Figure 6

C_IN

Input Capacitance

pF

3.30

Power Dissipation

Capacitance⁽⁴⁾

C_PD

pF

Figure 7

5.00

12

Note:

4.

C

_PDis defined as the value of the internal equivalent capacitance which is derived from dynamic operating

current consumption (I_CCD) at no output loading and operating at 50% duty cycle. C_PDis related to I_CCDdynamic

operating current by the expression: I_CCD=(C_PD)(V_CC)(f_IN)+(I_CCstatic).

Note:

5. CL includes load and stray capacitance;

Input PRR=1.0MHz; t_W=500ns

Figure 5. AC Test Circuit

Figure 6. AC Waveforms

Note:

6. Input=AC Waveform; t_r=t_f=1.8ns; PRR=10 MHz Duty Cycle=50%.

Figure 7. I_CCDTest Circuit

? 1999 Fairchild Semiconductor Corporation

www.fairchildsemi.com

NC7WZ16 ? Rev. 1.0.4

5

Physical Dimensions

SYMM

C

L

±0.20

2.00

A

0.65

0.50 MIN

6

4

B

PIN ONE

±0.10

1.25

1.90

1

3

0.30

0.15

(0.25)

0.40 MIN

0.10

A B

1.30

0.65

1.30

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.00

0.80

1.10

0.80

0.10

C

0.10

0.00

C

2.10±0.30

SEATING

PLANE

NOTES: UNLESS OTHERWISE SPECIFIED

GAGE

PLANE

A) THIS PACKAGE CONFORMS TO EIAJ

SC-88, 1996.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH.

(R0.10)

0.25

0.10

D) DRAWING FILENAME: MKT-MAA06AREV6

0.20

30°

0°

0.46

0.26

DETAIL A

SCALE: 60X

Figure 8. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

3000

Cavity Status Cover Type Status

Empty

Filled

Sealed

P6X

Trailer (Hub End)

75 (Typical)

Empty

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

6

Physical Dimensions

2X

0.05 C

1.45

B

(1)

2X

0.05 C

(0.49)

5X

(0.254)

1.00

(0.75)

(0.52)

1X

TOP VIEW

A

PIN 1 IDENTIFIER

5

0.55MAX

(0.30)

6X

PIN 1

0.05 C

0.05

0.00

RECOMMENED

LAND PATTERN

0.05 C

C

0.45

0.35

0.10

6X

0.00

0.25

6X

0.15

1.0

DETAIL A

0.10

C B A

0.40

0.30

0.05

C

0.35

0.25

5X

0.40

0.30

DETAIL A

PIN 1 TERMINAL

0.075 X 45

CHAMFER

0.5

BOTTOM VIEW

(0.05)

6X

(0.13)

4X

Notes:

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y14.5M-1994

4. FILENAME AND REVISION: MAC06AREV4

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 9. 6-Lead, MicroPak?, 1.0mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

L6X

Trailer (Hub End)

75 (Typical)

Empty

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

7

Physical Dimensions

0.89

0.35

0.05

C

1.00

B

A

2X

5X 0.40

1X 0.45

PIN 1

0.66

MIN 250uM

1.00

6X 0.19

0.05 C

TOP VIEW

RECOMMENDED LAND PATTERN

FOR SPACE CONSTRAINED PCB

2X

0.90

0.35

0.05 C

0.55MAX

C

5X 0.52

SIDE VIEW

0.73

0.57

1X

(0.08) 4X

DETAIL A

0.09

0.19

6X

1

2

3

0.20 6X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPLICATION

(0.05) 6X

0.35

5X

0.25

0.60

6

5

4

0.10

.05

C B A

0.40

0.30

0.35

(0.08)

4X

C

BOTTOM VIEW

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

B. DIMENSIONS ARE IN MILLIMETERS.

0.075X45°

CHAMFER

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

DESIGN.

DETAIL A

PIN 1 LEAD SCALE: 2X

E. DRAWING FILENAME AND REVISION: MGF06AREV3

Figure 10. 6-Lead, MicroPak2?, 1x1mm Body, .35mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

FHX

Trailer (Hub End)

75 (Typical)

Empty

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

8

? 1999 Fairchild Semiconductor Corporation

NC7WZ16 ? Rev. 1.0.4

www.fairchildsemi.com

9