AGC/UP-CONVERTER
WITH IQ MODULATOR
UPC8158K
INTERNAL BLOCK DIAGRAM
FEATURES
22
21 20 19 18 17 16 15
? SUPPLY VOLTAGE:
VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V
AGCcont
Up-Mix
23
24
25
14
13
12
? BUILT-IN LPF:
Suppresses spurious multipled by TX local (LO1)
AGC
Reg
Reg
LPF
? AGC AMPLIFIER INSTALLED IN LOCAL PORT OF
UPCONVERTER:
GCR = 35 dB MIN. @ fout = 1.5 GHz
26
27
11
10
9
I/Q-Mix
28
? EXCELLENT PERFORMANCE:
Phase
Shifter
Padj = -65dBc TYP. @ ?f = ±50 KHz, EVM = 1.2 %rms TYP.
1
2
3
4
5
6
7
8
? EXTERNAL IF FILTER:
Can be applied between modulator output and
up converter input terminal
DESCRIPTION
The UPC8158K is a silicon microwave monolithic integrated
circuit designed as a quadrature modulator for digital mobile
communication systems. This MMIC consist of a 0.8 GHz to
1.5 GHz up-converter and 100 MHz to 300 MHz quadrature
modulator which are equipped with AGC and power save
functions. This configuration suits IF modulation systems and
is packaged in a 28-pin QFN suitable for high density
mounting. The chip is manufactured using NEC's 20 GHz fT
silicon bipolar process NESATTM III to realize low power
consumption. Consequently the UPC8158K can contribute to
make RF blocks smaller size, higher performance and lower
power consumption.
APLICATIONS
? Digital cellular phones
(PDC800M, PDC1.5G,TDMA1900 and so on)
? Wireless Communiaction Systems
(MMDS, Broadband wireless access)
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V)
PART NUMBER
PACKAGE OUTLINE
UPC8158K
TYP
SYMBOLS
PARAMETERS AND CONDITIONS
UP-CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current, No input signal
UNITS
MIN
MAX
ICC (TOTAL)
mA
μA
23.7
28
0.3
-11.5
-52
-40
-40
-50
40
37.6
10
ICC(PS) TOTAL Total Circuit Current at Power Save Mode, VPS ≤ 0.5 V(low), No input signal
PRFout1
PRFout2
LOL
Total Output Power 1, VAGC = 2.5 V
dBm
dBm
dBc
dBc
dBc
dB
-15
-8
Total Output Power 2, VAGC = 1.0 V
-56.5
-46.5
-30
-30
-30
LO Carrier Leak, fLOL = fLO1 + fLO2
ImR
Image Rejection (Side Band Leak)
IM3(I/Q)
GCR
EVM
I/Q 3rd Order Distortion
AGC Gain Control Range, VAGC = 2 V →1 V
Error Vector Magnitude, MOD Pattern PN9
Adjacent Channel Interference, ?f = ±50KHz, MOD Pattern: PN9
35
80
%rms
dBc
dBc
μs
1.2
-65
-70
2
3.0
-60
-65
5
Padj
Pout(8fLO1) Spurious Suppression, fLO1 × 8, fLO1 × 8 (image)Note
TPS(Rise)
TPS(Fall)
ZI/Q
Power Save Rise Time, VPS(Low) → VPS(High)
Power Save Fall Time, VPS(High) → VPS(Low)
I/Q Input Impedance, Between pin I/Ib, Q/Qb
I/Q Input Bias Current, Between pin I/Ib, Q/Qb
LO1 Input VSWR, fLO1 = 100 M to 300 MHz
μs
2
5
k?
200
5
II/Q
μA
13
ZLO1
-
1.5 :1
Note:
1. Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
California Eastern Laboratories
